1. Field of the Invention
The present invention generally relates to a method of fabricating a field effect transistor, and more particularly, to a method of fabricating a multi-gate field effect transistor.
2. Description of the Prior Art
With the trend in the industry going towards scaling down the size of metal oxide semiconductor (MOS) transistors, three-dimensional or non-planar transistor technology has been developed to replace conventional planar MOS transistors.
In general, three-dimensional transistor devices could be of many kinds, such as dual-gate fin field effect transistors (dual-gate FinFETs), tri-gate field effect transistors (tri-gate FETs) and so forth, which allow tighter packing of the same number of transistors on a semiconductor chip by using vertical or tilted surfaces for the gates. For example, a dual-gate transistor comprises equal length gates situated along the sides of a narrow body, whereas a tri-gate transistor comprises three equal length gates situated on three exposed surfaces of a body. Whether in a dual-gate FinFET or a tri-gate FET, an overlapped region between a gate and a body in each FET can be increased effectively compared to conventional planar transistors. As a result, when a similar driving voltage is separately applied to a non-planar and a planar transistor, a current flowing through the channel regions of the non-planar transistor is often higher than that in the planar transistor.
An overall contact resistance of the tri-gate FET is a function of a contact resistance of the top gate and a contact resistance of each of the two side gates. The contact resistance at each gate is determined partly by the contact area of the source and drain, the materials used at the interface of the source and drain regions, such as a silicide layer, and the manner in which those materials interface. The silicide layer may be formed on the source and the drain regions for the top and side gates of a multi-gate FET to reduce the contact resistance, thereby increasing a FET current. The contact resistance can rise when a portion of the silicide material is blocked or is otherwise prevented from contacting a source or drain region.
There is still a need to provide a method of fabricating a non-planar (also called multi-gate) FET in order to overcome the above-mentioned drawbacks about high contact resistance.